Silicon carbide (silicon carbide: SiC) is a semiconductor material with a high hardness which has a greater band gap than that of silicon (Si), and is applied in various semiconductor devices such as power devices, environment resistant devices, high-temperature operating devices, and high-frequency devices. Among others, applications to power devices such as switching devices and rectifier devices are drawing attention. A power device in which SiC is used has an advantage of e.g. a greatly reduced power loss than that of an Si power device.
Among power devices in which SiC is used, representative switching devices are MOSFETs and MOSFETs. In such switching devices, based on a voltage which is applied to the gate electrode, it is possible to switch between an ON state where a drain current of several A (ampere) or more flows and an OFF state where there is zero drain current. Moreover, with SiC, a high breakdown voltage of several hundred V or more can be realized in the OFF state.
In such power devices, a structure is often adopted in which a current is allowed to flow in the front-rear direction of the substrate. Herein, the front face side is patterned by using a photoresist, whereas in most cases, an ohmic contact is formed on the essentially the entire surface of the rear face side.
A switching device structure using SiC is proposed in Patent Document 1, for example. Hereinafter, with reference to the drawings, the structure of a vertical MOSFET (a transistor in which a source electrode and a drain electrode are formed on opposite faces of the substrate) will be described.
FIG. 12A is a schematic cross-sectional view showing unit cells 1000 of a vertical MOSFET in which SiC is used, and FIG. 12B is a plan view showing the layout of component elements in a portion of the vertical MOSFET. FIG. 12A corresponds to a cross-sectional view as seen in the direction of arrows at line A-A′ in FIG. 12B. A vertical MOSFET typically includes a plurality of unit cells. FIG. 12A and FIG. 12B shows some unit cells 1000 among them.
As shown in FIG. 12A, a unit cell 1000 of a vertical MOSFET includes: a silicon carbide epitaxial layer 120 formed on a principal face of a low-resistance n type SiC substrate 101; a channel layer 106 formed on the silicon carbide epitaxial layer 120; a gate electrode 108 provided on the channel layer 106 via a gate insulating film 107; a source electrode 109 in contact with a surface 120s of the silicon carbide epitaxial layer; and a drain electrode 110 provided on the rear face of the SiC substrate 101.
FIG. 12B shows an exemplary layout of the gate electrode 108 and the source electrodes 109. This gate electrode 108 is made of an electrically conductive film covering a principal face of the SiC substrate 101, and includes a plurality of openings. A source electrode 109 is formed in the central portion of each of the plurality of openings. In FIG. 12B, a line surrounding each source electrode 109 shows the contour of a well region 103 described later. Each unit cell 1000 in the illustrated example includes one well region 103 and one source electrode 109.
The silicon carbide epitaxial layer 120 includes well regions 103 having a different conductivity type (which herein is the p type) from the conductivity type of the SiC substrate 101, and a drift region 102 which is composed of a portion of the silicon carbide epitaxial layer 120 where the well regions 103 are not formed. The drift region 102 is an n− type silicon carbide layer containing an n type impurity at a lower concentration than in the SiC substrate 101, for example.
Inside each well region 103, an n type source region 104 containing an n type impurity at a high concentration and a p+ type contact region 105 containing a p type impurity at a higher concentration than in the well region 103 are formed. The well regions 103, the source regions 104, and the contact regions 105 are formed through a step of implanting an impurity into the silicon carbide epitaxial layer 120 and a high-temperature heat treatment (activation anneal) step of activating the impurity which has been implanted into the silicon carbide epitaxial layer 120.
The source regions 104 and the drift region 102 are connected via the channel layer 106. The channel layer 106 is a 4H-SiC layer which is formed on the silicon carbide epitaxial layer 102 through epitaxial growth, for example.
Each contact region 105 and each source region 104 constitute an ohmic contact with a source electrode 109. Thus, the well region 103 is electrically connected with the source electrode 109 via the contact region 105.
The source electrodes 109 can be formed by, after forming an electrically conductive material (Ni) layer on the source regions 104 and the contact regions 105 of the silicon carbide epitaxial layer 120, performing a heat treatment at a high temperature. Generally speaking, a heat treatment at a high temperature of about 1000° C. is performed (Post Deposition Annealing technique) to obtain the source electrodes 109. According to this method, a reaction layer is formed through the high-temperature heat treatment at the interfaces between the electrically conductive material layer and the source regions 104 and the contact regions 105, and therefore the resultant source electrodes 109 have good ohmic characteristics with respect to these regions 104 and 105. More specifically, it is presumable that, when Ni is adopted as the material for the source electrode, Ni reacts with the Si within the silicon carbide to form Ni silicide, and the C within the silicon carbide is taken into the Ni silicide film, so that an impurity level that is ascribable to C is formed at the interface between Ni silicide and silicon carbide, whereby an ohmic contact is formed.
The gate insulating film 107 is a thermal oxide film (SiO2 film) which is formed by subjecting the surface of the channel layer 106 to thermal oxidation, for example. The gate electrode 108 is formed by using an electrically conductive polysilicon, for example. The gate electrode 108 is common to the respective unit cells, and is connected to an external circuit via one gate electrode pad (not shown). A gate signal is to be supplied to the gate electrode 108 through this gate electrode pad.
The gate electrode 108 is covered by an interlayer insulating film 111. Openings 113 are formed in the interlayer insulating film 111, such that the source electrodes 109 of the respective unit cells are connected in parallel to an upper electrode layer (e.g. an Al electrode) 112 through the openings 113.
Ohmic characteristics are also required of the drain electrode 110. Again, Ni is adopted for the drain electrode 110; after forming Ni on the rear face of the silicon carbide substrate 101, a heat treatment at a high temperature of about 1000° C. is performed to obtain the drain electrode 110. On the surface (corresponding to the lower side of the drain electrode 110 in FIG. 12A) of the drain electrode, a rear face electrode 130 for assembly into a package is further formed. The rear face electrode 130 has a multilayer structure in most cases.
[Patent Document 1] Japanese National Phase PCT Laid-Open Publication No. 2004-519842